YakmoijebrilleShaared links2022-01-21T09:15:19+01:00Yakmoijebrillehttp://fabienm.eu/shaarli/http://fabienm.eu/shaarli/Shaarli* import chisel3._ class Example extends Module { val a, b, c = IO(Input(Bool())) val d, e, f = IO(Input(Bool())) val foo, bar = IO(Input(UInt(8.W))) val out = IO(Output(UInt(8.W))) val myReg = RegInit(0.U(8.W)) out := myReg when (a && b && c) { myReg := foo } when (d && e && f) { myReg := bar } } println(getVerilogString(new Example)) - Scastiehttp://fabienm.eu/shaarli/shaare/CPzCdw2022-01-21T09:15:19+01:002022-01-21T09:15:19+01:00