5 private links
(Icarus + Ngspice) + cocotb = SpiceBind !
SpiceBind – spice inside HDL simulator. Contribute to themperek/spicebind development by creating an account on GitHub.
Open Logic se veut être la stdlib du VHDL
Un générateur arithmetic de core.
Spade is a hardware description language inspired by modern software languages.
This repository contains a fast VHDL language server and analysis library written in Rust.
The speed makes the tool very pleasant to use since it loads projects really fast and does not consume a lot of ram. A 200.000 line VHDL project is analyzed in 160 ms on my Desktop using 8 cores and only consumes 180 MByte of RAM when loaded.
I very much appreciate help from other people especially regarding semantic analysis of VHDL. You do not need to be a programmer to help, it is even more helpful to interpret and clarify the VHDL standard and provide minimal examples and describe how they should work according to the standard. Further information about contributing can be found by reading the Contributors Guide
In what was a major achievement in open source FPGA development, we have now added support for the largest FPGA so far supported by open source tooling! 500,000 LUTs!\nIn November 2024 we successfully concluded the European Space Agency funded project in collaboration with NanoExplore, known for their space rated FPGAs.\nThe tool provides developers with a flexible and customizable option for designing for NG-Ultra FPGAs, offering increased reliability through the ability to cross-verify designs using two independent tools.\n
La branche gatemate de nextpnr
Une doc de CologneChip sur comment s'interfacer en 3v3 avec son FPGA
Ho, Un projet de portage du gatemate sur NextPnR !
\o/
Un projet d'exemple en Clash
Un HDL qui ne donne pas envie de s'arracher les cheveux. Inspiré de Rust et Clash. Hmm à voir.
This repository shows how to convert a complex VHDL design into a single, synthesizable, plain-Verilog module using GHDL's synthesis feature.
Appeler du python depuis du SystemVerilog.
Une carte de développement FPGA (ICE40) au format ... microsd !
Un analyseur syntaxique VHDL écrit en rust. Disponible pour VSCode, Emacs, NeoVim, ...
Un cours complet sur l'analyse static des timings.
Renesas SLG7EVBFORGE FPGA dev board, built around SLG47910V is Renesas' first low-density FPGA in the ForgeFPGA family. The FPGA includes 1120 LUTs, 1120
