chisverilogutils: Chisel, Cocotb, smtbmc toolkit
If you are designing your gateware with Chisel-HDL and testing it with CocoTB, you will need some script like that.
Wed Jan 29 15:16:12 2020 - permalink -
- to add waveform under verilog TOP generated for Icarus simulation
- To generate all cocotb files for testing a Chisel module
- To inject some SystemVerilog code in verilog generated for Formal verification (assume/assert/cover/...)