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November 20, 2024

stnolting/neorv32-verilog: ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

This repository shows how to convert a complex VHDL design into a single, synthesizable, plain-Verilog module using GHDL's synthesis feature.

flf vhdl fpga riscv