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Week 03 (January 17, 2022)

Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning - AB Open

Google publie le code d'un outil pour faire du «floorplanning» avec de l'IA.
En plus d'être open-source, l'outil est incroyablement plus performant que l'humain pour la conception d'ASIC (et de FPGA ?)

flf google ia asic fpga floorplanning
Machine Learning Detects Distracted Politicians | Hackaday

De l'IA pour fliquer les parlementaire. J'adore ;)

politique IA video
import chisel3._ import chisel3.stage.ChiselStage class Foo extends Module { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) io.out := ~io.in } println((new ChiselStage).emitVerilog(new Foo)) - Scastie

Pour tester des bouts de code Chisel en ligne

chisel flf scastie online web scala
GPS – Bartosz Ciechanowski

Comment marche le GPS, explication complète en Images.

science GPS math radio électronique
CharaChorder - Type at the Speed of Thought - Peripheral Device

Un nouveau concept révolutionnaire de clavier ?

clavier charachorder
Building a SoC with Litex. – controlpaths.

Construire un SoC (System on Chip) en 5 minutes avec Litex.

flf litex soc python fpga
brianbennett/fpga_nes: FPGA-based Nintendo Entertainment System Emulator
fdf nes fpga verilog
* import chisel3._ class Example extends Module { val a, b, c = IO(Input(Bool())) val d, e, f = IO(Input(Bool())) val foo, bar = IO(Input(UInt(8.W))) val out = IO(Output(UInt(8.W))) val myReg = RegInit(0.U(8.W)) out := myReg when (a && b && c) { myReg := foo } when (d && e && f) { myReg := bar } } println(getVerilogString(new Example)) - Scastie

Chisel version 3.5.0 sur scatie

scatie flf chisel scala