import chisel3._ import chisel3.stage.ChiselStage class Foo extends Module { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) io.out := ~io.in } println((new ChiselStage).emitVerilog(new Foo)) - Scastie
Mon Jan 17 09:03:12 2022 - permalink - - https://scastie.scala-lang.org/nG8DwNJXSoy4jseHUaRa3w