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  • 'WBCLKI' must be connected to an active clock source")
    4. Sadly IPEXPRESS generates a malfunctional EFB module (at least if verilog is selected) if only I2C configuration (without WISHBONE) is selected. As long as the Lattice support keeps ignoring reports about that a workaround is required. On the bright side this is not that tough. After module generation one simple opens the corresponding .v file and  add an input wire e.g. wb_clk_in. Then replace ".WBCLKI(scuba_vlo)" by ".WBCLKI(wb_clk_in)" and make sure that a clock with appropriate frequency is connected to wb_clk_in (WISHBONE clock frequency can be modified in IPEXPRESS during EFB instantiation).
    Thu Jul 26 14:02:37 2018 - permalink -
    - http://buildingelectronics.blogspot.com/2017/09/machxo3lf-tips-tricks.html
    EFB flf fpga i2c lattice machxo3 verilog wishbone
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