«FPGAParadox focuses on R&D related to FPGAs, digital design (preferably in SystemVerilog), and formal verification techniques. We have experience with industrial tools (Synopsys, Cadence, Siemens EDA) and OpenSource Tabby CAD.

This site is maintained by Diego Hdez <dhdezr [at] fpgaparadox [dot] com>. Diego also collaborates with YosysHQ and with DRISC Logic.»