5330 shaares
5 private links
5 private links
If you are designing your gateware with Chisel-HDL and testing it with CocoTB, you will need some script like that.
- to add waveform under verilog TOP generated for Icarus simulation
- To generate all cocotb files for testing a Chisel module
- To inject some SystemVerilog code in verilog generated for Formal verification (assume/assert/cover/...)
